Synopsys Design Compiler Tutorial 2021
Synopsys Design Compiler Tutorial (2021 Edition): A Comprehensive Guide to Logic Synthesis
# Timing report report_timing -delay_type max -nworst 10 > reports/timing.rpt
- Create a design directory and gather required files (e.g., RTL code, constraint files)
- Write a simple RTL code (e.g., a counter)
Step 4: Applying Constraints (SDC 3.0)
3.3 Using the New Python API
Chapter 2: The Synthesis Flow Overview
